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d a t a sh eet product speci?cation 2002 may 22 integrated circuits UDA1334BT low power audio dac
2002 may 22 2 philips semiconductors product speci?cation low power audio dac UDA1334BT contents 1 features 1.1 general 1.2 multiple format data interface 1.3 dac digital sound processing 1.4 advanced audio configuration 2 applications 3 general description 4 ordering information 5 quick reference data 6 block diagram 7 pinning 8 functional description 8.1 system clock 8.2 interpolation filter 8.3 noise shaper 8.4 filter stream dac 8.5 power-on reset 8.6 feature settings 8.6.1 digital interface format select 8.6.2 mute control 8.6.3 de-emphasis control 8.6.4 power control and sampling frequency select 9 limiting values 10 handling 11 thermal characteristics 12 quality specification 13 dc characteristics 14 ac characteristics 14.1 2.0 v supply voltage 14.2 3.0 v supply voltage 14.3 timing 15 application information 16 package outline 17 soldering 17.1 introduction to soldering surface mount packages 17.2 reflow soldering 17.3 wave soldering 17.4 manual soldering 17.5 suitability of surface mount ic packages for wave and reflow soldering methods 18 data sheet status 19 definitions 20 disclaimers
2002 may 22 3 philips semiconductors product speci?cation low power audio dac UDA1334BT 1 features 1.1 general 1.8 to 3.6 v power supply voltage integrated digital filter plus dac supports sample frequencies from 8 to 100 khz automatic system clock versus sample rate detection low power consumption no analog post filtering required for dac slave mode only applications easy application so16 package. 1.2 multiple format data interface i 2 s-bus and lsb-justified format compatible 1f s input data rate. 1.3 dac digital sound processing digital de-emphasis for 44.1 khz sampling rate mute function. 1.4 advanced audio con?guration high linearity, wide dynamic range and low distortion standby or sleep mode in which the dac is powered down. 2 applications this audio dac is excellently suitable for digital audio portable application, such as portable md, mp3 and dvd players. 3 general description the UDA1334BT supports the i 2 s-bus data format with word lengths of up to 24 bits and the lsb-justified serial data format with word lengths of 16, 20 and 24 bits. the UDA1334BT has basic features such as de-emphasis (at 44.1 khz sampling rate) and mute. 4 ordering information type number package name description version UDA1334BT so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1
2002 may 22 4 philips semiconductors product speci?cation low power audio dac UDA1334BT 5 quick reference data note 1. the dac output voltage scales proportionally to the power supply voltage. symbol parameter conditions min. typ. max. unit supplies v dda dac analog supply voltage 1.8 2.0 3.6 v v ddd digital supply voltage 1.8 2.0 3.6 v i dda dac analog supply current normal operating mode - 2.3 - ma sleep mode - 125 -m a i ddd digital supply current normal operating mode - 1.4 - ma sleep mode clock running - 250 -m a no clock running - 20 -m a t amb ambient temperature - 40 - +85 c digital-to-analog converter (v dda =v ddd = 2.0 v) v o(rms) output voltage (rms value) at 0 db (fs) digital input; note 1 - 600 - mv (thd + n)/s total harmonic distortion-plus-noise to signal ratio f s = 44.1 khz; at 0 db -- 80 - db f s = 44.1 khz; at - 60 db; a-weighted -- 37 - db f s = 96 khz; at 0 db -- 75 - db f s = 96 khz; at - 60 db; a-weighted -- 35 - db s/n signal-to-noise ratio f s = 44.1 khz; code = 0; a-weighted - 97 - db f s = 96 khz; code = 0; a-weighted - 95 - db a cs channel separation - 100 - db digital-to-analog converter (v dda =v ddd = 3.0 v) v o(rms) output voltage (rms value) at 0 db (fs) digital input; note 1 - 900 - mv (thd + n)/s total harmonic distortion-plus-noise to signal ratio f s = 44.1 khz; at 0 db -- 90 - db f s = 44.1 khz; at - 60 db; a-weighted -- 40 - db f s = 96 khz; at 0 db -- 85 - db f s = 96 khz; at - 60 db; a-weighted -- 37 - db s/n signal-to-noise ratio f s = 44.1 khz; code = 0; a-weighted - 100 - db f s = 96 khz; code = 0; a-weighted - 98 - db a cs channel separation - 100 - db power dissipation (at f s = 44.1 khz) p power dissipation playback mode at 2.0 v supply voltage - 7.4 - mw at 3.0 v supply voltage - 17 - mw sleep mode; at 2.0 v supply voltage clock running - 0.75 - mw no clock running - 0.3 - mw
2002 may 22 5 philips semiconductors product speci?cation low power audio dac UDA1334BT 6 block diagram handbook, full pagewidth mgu676 dac UDA1334BT noise shaper interpolation filter de-emphasis 14 15 dac 6 digital interface 16 3 2 1 4 5 11 7 13 12 voutr bck v ssa ws voutl datai v dda v ddd v ref(dac) v ssd sfor0 sysclk 8 mute 9 deem 10 pcs sfor1 fig.1 block diagram.
2002 may 22 6 philips semiconductors product speci?cation low power audio dac UDA1334BT 7 pinning notes 1. 5 v tolerant is only supported if the power supply voltage is between 2.7 and 3.6 v. for lower power supply voltages this is maximum 3.3 v tolerant. 2. because of test issues these pads are not 5 v tolerant and they should be at power supply voltage level or at a maximum of 0.5 v above that level. symbol pin pad type description bck 1 5 v tolerant digital input pad; note 1 bit clock input ws 2 5 v tolerant digital input pad; note 1 word select input datai 3 5 v tolerant digital input pad; note 1 serial data input v ddd 4 digital supply pad digital supply voltage v ssd 5 digital ground pad digital ground sysclk 6 5 v tolerant digital input pad; note 1 system clock input sfor1 7 5 v tolerant digital input pad; note 1 serial format select 1 mute 8 5 v tolerant digital input pad; note 1 mute control deem 9 5 v tolerant digital input pad; note 1 de-emphasis control pcs 10 3-level input pad; note 2 power control and sampling frequency select sfor0 11 digital input pad; note 2 serial format select 0 v ref(dac) 12 analog pad dac reference voltage v dda 13 analog supply pad dac analog supply voltage voutl 14 analog output pad dac output left v ssa 15 analog ground pad dac analog ground voutr 16 analog output pad dac output right handbook, halfpage mgu675 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 voutr bck v ssa ws voutl datai v dda v ddd v ref(dac) v ssd sfor0 sysclk pcs sfor1 deem mute UDA1334BT fig.2 pin configuration.
2002 may 22 7 philips semiconductors product speci?cation low power audio dac UDA1334BT 8 functional description 8.1 system clock the UDA1334BT operates in slave mode only; this means that in all applications the system must provide the system clock and the digital audio interface signals (bck and ws). the system clock must be locked in frequency to the digital interface signals. the UDA1334BT automatically detects the ratio between the sysclk and ws frequencies. the bck clock can be up to 64f s , or in other words the bck frequency is 64 times the word select (ws) frequency or less: f bck 64 f ws . remarks: 1. the ws edge must fall on the negative edge of the bck at all times for proper operation of the digital i/o data interface 2. for lsb-justified formats it is important to have a ws signal with a duty factor of 50%. the modes which are supported are given in table 1. table 1 supported sampling ranges notes 1. this mode can only be supported for power supply voltages down to 2.4 v. for lower voltages, in 192f s mode the sampling frequency should be limited to 55 khz. 2. not supported in the low sampling frequency mode. an example is given in table 2 for a 12.228 mhz system clock input. table 2 example using a 12.228 mhz system clock note 1. this mode can only be supported for power supply voltages down to 2.4 v. for lower voltages, in 192f s mode the sampling frequency should be limited to 55 khz. 8.2 interpolation ?lter the interpolation digital filter interpolates from 1f s to 64f s by cascading fir filters (see table 3). table 3 interpolation ?lter characteristics 8.3 noise shaper the 5th-order noise shaper operates at 64f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted into an analog signal using a filter stream dac (fsdac). clock mode sampling range 768f s 8to55khz 512f s 8 to 100 khz 384f s 8 to 100 khz 256f s 8 to 100 khz 192f s 8 to 100 khz (1)(2) 128f s 8 to 100 khz (2) clock mode sampling frequency 128f s 96 khz 192f s 64 khz (1) 256f s 48 khz 384f s 32 khz 512f s 24 khz 768f s 16 khz item condition value (db) pass-band ripple 0 to 0.45f s 0.02 stop band >0.55f s - 50 dynamic range 0 to 0.45f s >114
2002 may 22 8 philips semiconductors product speci?cation low power audio dac UDA1334BT 8.4 filter stream dac the fsdac is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. no post-filter is needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output. the output voltage of the fsdac scales proportionally with the power supply voltage. 8.5 power-on reset the UDA1334BT has an internal power-on reset circuit (see fig.3) which resets the test control block. the reset time (see fig.4) is determined by an external capacitor which is connected between pin v ref(dac) and ground. the reset time should be at least 1 m s for v ref(dac) < 1.25 v. when v dda is switched off, the device will be reset again for v ref(dac) < 0.75 v. during the reset time the system clock should be running. handbook, halfpage v dda v ref(dac) 3.0 v 13 12 mgu678 UDA1334BT c1 > 10 m f reset circuit 50 k w 50 k w fig.3 power-on reset circuit. handbook, halfpage 3.0 v ddd (v) 1.5 0 t 3.0 v dda (v) 1.5 0 t 3.0 v ref(dac) (v) 1.5 1.25 0.75 0 t mgl984 > 1 m s fig.4 power-on reset timing.
2002 may 22 9 philips semiconductors product speci?cation low power audio dac UDA1334BT 8.6 feature settings the features of the UDA1334BT can be set by control pins sfor1, sfor0, mute, deem and pcs. 8.6.1 d igital interface format select the digital audio interface formats (see fig.5) can be selected via the pins sfor1 and sfor0 as shown in table 4. table 4 data format selection 8.6.2 m ute control the output signal can be soft muted by setting pin mute to high level as shown in table 5. table 5 mute control 8.6.3 d e - emphasis control de-emphasis can be switched on for f s = 44.1 khz by setting pin deem at high level. the function description of pin deem is given in table 6. table 6 de-emphasis control remark: the de-emphasis function in only supported in the normal operating mode, not in the low sampling frequency mode. 8.6.4 p ower control and sampling frequency select pin pcs is a 3-level pin and is used to set the mode of the UDA1334BT. the definition is given in table 7. table 7 pcs function de?nition the low sampling frequency mode is required to have a higher oversampling rate in the noise shaper in order to improve the signal-to-noise ratio. in this mode the oversampling ratio of the noise shaper will be 128f s instead of 64f s . sfor1 sfor0 input format low low i 2 s-bus input low high lsb-justi?ed 16 bits input high low lsb-justi?ed 20 bits input high high lsb-justi?ed 24 bits input mute function low mute off high mute on deem function low de-emphasis off high de-emphasis on pcs function low normal operating mode mid low sampling frequency mode high power-down or sleep mode
2002 may 22 10 philips semiconductors product speci?cation low power audio dac UDA1334BT this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mgs752 16 b5 b6 b7 b8 b9 b10 left lsb-justified format 24 bits ws bck data right 15 18 17 20 19 22 21 23 24 2 1 b3 b4 msb b2 b23 lsb 16 b5 b6 b7 b8 b9 b10 15 18 17 20 19 22 21 23 24 21 b3 b4 msb b2 b23 lsb 16 msb b2 b3 b4 b5 b6 left lsb-justified format 20 bits ws bck data right 15 18 17 20 19 2 1 b19 lsb 16 msb b2 b3 b4 b5 b6 15 18 17 20 19 2 1 b19 lsb 16 msb b2 left lsb-justified format 16 bits ws bck data right 15 2 1 b15 lsb 16 msb b2 15 2 1 b15 lsb msb msb b2 2 1 > = 8 12 3 left i 2 s-bus format ws bck data right 3 > = 8 msb b2 fig.5 digital audio formats
2002 may 22 11 philips semiconductors product speci?cation low power audio dac UDA1334BT 9 limiting values in accordance with the absolute maximum rating system (iec 60134). note 1. all supply connections must be made to the same power supply. 2. short-circuit test at t amb =0 c and v dda = 3 v. dac operation after short-circuiting cannot be warranted. 10 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, it is good practice to take normal precautions appropriate to handling mos devices. 11 thermal characteristics 12 quality specification in accordance with snw-fq-611-d . 13 dc characteristics v ddd =v dda = 2.0 v; t amb =25 c; r l =5k w ; all voltages with respect to ground (pins v ssa and v ssd ); unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage note 1 - 4.0 v t xtal(max) maximum crystal temperature - 150 c t stg storage temperature - 65 +125 c t amb ambient temperature - 40 +85 c v es electrostatic handling voltage human body model - 2000 +2000 v machine model - 200 +200 v i sc(dac) short-circuit current of dac note 2 output short-circuited to v ssa - 450 ma output short-circuited to v dda - 300 ma symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 145 k/w symbol parameter conditions min. typ. max. unit supplies v dda dac analog supply voltage note 1 1.8 2.0 3.6 v v ddd digital supply voltage note 1 1.8 2.0 3.6 v i dda dac analog supply current normal operating mode at 2.0 v supply voltage - 2.3 - ma at 3.0 v supply voltage - 3.5 - ma sleep mode at 2.0 v supply voltage - 125 -m a at 3.0 v supply voltage - 175 -m a
2002 may 22 12 philips semiconductors product speci?cation low power audio dac UDA1334BT notes 1. all supply connections must be made to the same external power supply unit. 2. at 3 v supply voltage, the input pads are ttl compatible. however, at 2.0 v supply voltage no ttl levels can be accepted, but levels from 3.3 v domain can be applied to the pins. 3. when the dac drives a capacitive load above 50 pf, a series resistance of 100 w must be used to prevent oscillations in the output operational amplifier. i ddd digital supply current normal operating mode at 2.0 v supply voltage - 1.4 - ma at 3.0 v supply voltage - 2.1 - ma sleep mode; at 2.0 v supply voltage clock running - 250 -m a no clock running - 20 -m a sleep mode; at 3.0 v supply voltage clock running - 375 -m a no clock running - 30 -m a digital input pins; note 2 v ih high-level input voltage at 2.0 v supply voltage 1.3 - 3.3 v at 3.0 v supply voltage 2.0 - 5.0 v v il low-level input voltage at 2.0 v supply voltage - 0.5 - +0.5 v at 3.0 v supply voltage - 0.5 - +0.8 v ? i li ? input leakage current -- 1 m a c i input capacitance -- 10 pf 3-level input: pin pcs v ih high-level input voltage 0.9v ddd - v ddd + 0.5 v v im mid-level input voltage 0.4v ddd - 0.6v ddd v v il low-level input voltage - 0.5 - +0.5 v dac v ref(dac) reference voltage with respect to v ssa 0.45v dda 0.5v dda 0.55v dda v r o(ref) output resistance on pin v ref(dac) - 25 - k w i o(max) maximum output current (thd + n)/s < 0.1%; r l = 800 w - 1.6 - ma r l load resistance 3 -- k w c l load capacitance note 3 -- 50 pf symbol parameter conditions min. typ. max. unit
2002 may 22 13 philips semiconductors product speci?cation low power audio dac UDA1334BT 14 ac characteristics 14.1 2.0 v supply voltage v ddd =v dda = 2.0 v; f i = 1 khz; t amb =25 c; r l =5k w .; all voltages with respect to ground (pins v ssa and v ssd ); unless otherwise speci?ed. 14.2 3.0 v supply voltage v ddd =v dda = 3.0 v; f i = 1 khz; t amb =25 c; r l =5k w ; all voltages with respect to ground (pins v ssa and v ssd ); unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit dac v o(rms) output voltage (rms value) at 0 db (fs) digital input - 600 - mv d v o unbalance between channels - 0.1 - db (thd + n)/s total harmonic distortion-plus-noise to signal ratio f s = 44.1 khz; at 0 db -- 80 - db f s = 44.1 khz; at - 60 db; a-weighted -- 37 - db f s = 96 khz; at 0 db -- 75 - db f s = 96 khz; at - 60 db; a-weighted -- 35 - db s/n signal-to-noise ratio f s = 44.1 khz; code = 0; a-weighted - 97 - db f s = 96 khz; code = 0; a-weighted - 95 - db a cs channel separation - 100 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple = 30 mv (p-p) - 60 - db symbol parameter conditions min. typ. max. unit dac v o(rms) output voltage (rms value) at 0 db (fs) digital input - 900 - mv d v o unbalance between channels - 0.1 - db (thd + n)/s total harmonic distortion-plus-noise to signal ratio f s = 44.1 khz; at 0 db -- 90 - db f s = 44.1 khz; at - 60 db; a-weighted -- 40 - db f s = 96 khz; at 0 db -- 85 - db f s = 96 khz; at - 60 db; a-weighted -- 37 - db s/n signal-to-noise ratio f s = 44.1 khz; code = 0; a-weighted - 100 - db f s = 96 khz; code = 0; a-weighted - 98 - db a cs channel separation - 100 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple = 30 mv (p-p) - 60 - db
2002 may 22 14 philips semiconductors product speci?cation low power audio dac UDA1334BT 14.3 timing v ddd =v dda = 1.8 to 3.6 v; t amb = - 20 to +85 c; r l =5k w ; all voltages with respect to ground (pins v ssa and v ssd ); unless otherwise speci?ed; note 1. note 1. the typical value of the timing is specified at f s = 44.1 khz (sampling frequency). symbol parameter conditions min. typ. max. unit system clock timing (see fig.6) t sys system clock cycle time f sys = 256f s 35 88 780 ns f sys = 384f s 23 59 520 ns f sys = 512f s 17 44 390 ns t cwh system clock high time f sys < 19.2 mhz 0.3t sys - 0.7t sys ns f sys 3 19.2 mhz 0.4t sys - 0.6t sys ns t cwl system clock low time f sys < 19.2 mhz 0.3t sys - 0.7t sys ns f sys 3 19.2 mhz 0.4t sys - 0.6t sys ns reset timing t reset reset time 1 --m s serial interface timing (see fig.7) f bck bit clock frequency -- 64f s hz t bckh bit clock high time 50 -- ns t bckl bit clock low time 50 -- ns t r rise time -- 20 ns t f fall time -- 20 ns t su(datai) set-up time data input 20 -- ns t h(datai) hold time data input 0 -- ns t su(ws) set-up time word select 20 -- ns t h(ws) hold time word select 10 -- ns
2002 may 22 15 philips semiconductors product speci?cation low power audio dac UDA1334BT handbook, full pagewidth mgr984 t sys t cwh t cwl fig.6 system clock timing. handbook, full pagewidth mgl880 t f t h(ws) t su(ws) t su(datai) t h(datai) t bckh t bckl t cy(bck) t r ws bck datai fig.7 serial interface timing.
2002 may 22 16 philips semiconductors product speci?cation low power audio dac UDA1334BT 15 application information handbook, full pagewidth mgu677 47 w r5 UDA1334BT 6 sysclk system clock 1 bck 2 ws 3 datai 14 voutl r3 100 w r1 220 k w 16 voutr r4 100 w r2 220 k w 7 sfor1 11 sfor0 9 deem 10 pcs 8 mute 47 m f (16 v) c4 47 m f (16 v) c3 left output right output 12 v ref(dac) c7 47 m f (16 v) c8 100 nf (63 v) 4 5 v ddd v ssd r6 1 w digital supply voltage c6 15 13 v ssa v dda r7 1 w c9 47 m f (16 v) c10 100 nf (63 v) 100 nf (63 v) analog supply voltage c5 47 m f (16 v) c1 10 nf (63 v) 10 nf (63 v) c2 fig.8 typical application diagram.
2002 may 22 17 philips semiconductors product speci?cation low power audio dac UDA1334BT 16 package outline x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 sot109-1 97-05-22 99-12-27 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.050 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
2002 may 22 18 philips semiconductors product speci?cation low power audio dac UDA1334BT 17 soldering 17.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 17.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 17.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2002 may 22 19 philips semiconductors product speci?cation low power audio dac UDA1334BT 17.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2002 may 22 20 philips semiconductors product speci?cation low power audio dac UDA1334BT 18 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 19 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 may 22 21 philips semiconductors product speci?cation low power audio dac UDA1334BT notes
2002 may 22 22 philips semiconductors product speci?cation low power audio dac UDA1334BT notes
2002 may 22 23 philips semiconductors product speci?cation low power audio dac UDA1334BT notes
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753503/01/pp 24 date of release: 2002 may 22 document order number: 9397 750 09744

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